A hardware implementation of punctured convolutional codes to complete a Viterbi decoder core
This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes. We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n with the constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit was designed in order to complete an existing Viterbi decoder core, adding some extra functionality such as a convolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion to depuncture the received data. This extra functionality includes 10 different programmable coding rates without the need to add additional logic in the system implementation, while other existing coders need it to attain higher coding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High Speed Integrated Circuit Hardware Description Language) synthesized in Synopsystool, and tested in a FPGA. Functional verification was done, by means of simulation, to ensure that the circuit implements intended functionality. Such simulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probability performance curves show an agreement between simulated and theoretical values.
| Main Authors: | , , |
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| Format: | Digital revista |
| Language: | English |
| Published: |
Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología
2005
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| Online Access: | http://www.scielo.org.mx/scielo.php?script=sci_arttext&pid=S1665-64232005000200001 |
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| Summary: | This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes. We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n with the constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit was designed in order to complete an existing Viterbi decoder core, adding some extra functionality such as a convolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion to depuncture the received data. This extra functionality includes 10 different programmable coding rates without the need to add additional logic in the system implementation, while other existing coders need it to attain higher coding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High Speed Integrated Circuit Hardware Description Language) synthesized in Synopsystool, and tested in a FPGA. Functional verification was done, by means of simulation, to ensure that the circuit implements intended functionality. Such simulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probability performance curves show an agreement between simulated and theoretical values. |
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