The Verilog® Hardware Description Language [electronic resource] /

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

Bibliographic Details

Main Authors:	Thomas, Donald E. author., Moorby, Philip R. author., SpringerLink (Online service)
Format:	Texto biblioteca
Language:	eng
Published:	Boston, MA : Springer US : Imprint: Springer, 1991
Subjects:	Engineering., Computer hardware., Computer-aided engineering., Electrical engineering., Electronic circuits., Circuits and Systems., Electrical Engineering., Computer-Aided Engineering (CAD, CAE) and Design., Computer Hardware.,
Online Access:	http://dx.doi.org/10.1007/978-1-4615-3992-6
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