Design and evaluation of energy-efficient carbon nanotube FET-based quaternary minimum and maximum circuits
Abstract This article presents energy-efficient quaternary minimum and maximum logic circuits based on carbon nanotube field-effect transistor (CNTFET). The specific features of CNTFET, such as the possibility of determining the desired threshold voltages which are obtained by acquiring suitable diameters for carbon nanotubes, facilitate designing efficient circuits with multiple threshold voltages. The proposed mínimum and maximum circuits are designed using an efficient combination of quaternary multiplexers and specific ternary buffers. The proposed designs are simulated using Synopsys HSPICE with the Stanford 32 nm CNTFET technology and the performance parameters and sensitivity to process and temperature variations are evaluated through comprehensive simulations. The results demonstrate that the proposed QMin and QMax designsoperate with high robustness even in the presence of major process variations. In addition, they have 51% and 63% lower power-delay product (PDP) and 64% and 61% lower energy-delay product (EDP), respectively, as compared to the state-of-the-art CNTFET-based quaternary circuitsrecently presented in the literature.
Main Authors: | , , , |
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Format: | Digital revista |
Language: | English |
Published: |
Universidad Nacional Autónoma de México, Instituto de Ciencias Aplicadas y Tecnología
2017
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Online Access: | http://www.scielo.org.mx/scielo.php?script=sci_arttext&pid=S1665-64232017000300233 |
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Summary: | Abstract This article presents energy-efficient quaternary minimum and maximum logic circuits based on carbon nanotube field-effect transistor (CNTFET). The specific features of CNTFET, such as the possibility of determining the desired threshold voltages which are obtained by acquiring suitable diameters for carbon nanotubes, facilitate designing efficient circuits with multiple threshold voltages. The proposed mínimum and maximum circuits are designed using an efficient combination of quaternary multiplexers and specific ternary buffers. The proposed designs are simulated using Synopsys HSPICE with the Stanford 32 nm CNTFET technology and the performance parameters and sensitivity to process and temperature variations are evaluated through comprehensive simulations. The results demonstrate that the proposed QMin and QMax designsoperate with high robustness even in the presence of major process variations. In addition, they have 51% and 63% lower power-delay product (PDP) and 64% and 61% lower energy-delay product (EDP), respectively, as compared to the state-of-the-art CNTFET-based quaternary circuitsrecently presented in the literature. |
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