Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Bibliographic Details

Main Authors:	Umamageswaran, Kothanda. author., Pandey, Sheetanshu L. author., Wilsey, Philip A. author., SpringerLink (Online service)
Format:	Texto biblioteca
Language:	eng
Published:	Boston, MA : Springer US : Imprint: Springer, 1999
Subjects:	Engineering., Computer hardware., Computer-aided engineering., Electrical engineering., Electronic circuits., Circuits and Systems., Computer Hardware., Computer-Aided Engineering (CAD, CAE) and Design., Electrical Engineering.,
Online Access:	http://dx.doi.org/10.1007/978-1-4615-5123-2
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