Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /

Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /

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Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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Bibliographic Details
Main Authors: Umamageswaran, Kothanda. author., Pandey, Sheetanshu L. author., Wilsey, Philip A. author., SpringerLink (Online service)
Format: Texto biblioteca
Language:eng
Published: Boston, MA : Springer US : Imprint: Springer, 1999
Subjects:Engineering., Computer hardware., Computer-aided engineering., Electrical engineering., Electronic circuits., Circuits and Systems., Computer Hardware., Computer-Aided Engineering (CAD, CAE) and Design., Electrical Engineering.,
Online Access:http://dx.doi.org/10.1007/978-1-4615-5123-2
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id KOHA-OAI-TEST:194972
record_format koha
institution COLPOS
collection Koha
country México
countrycode MX
component Bibliográfico
access En linea
En linea
databasecode cat-colpos
tag biblioteca
region America del Norte
libraryname Departamento de documentación y biblioteca de COLPOS
language eng
topic Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer Hardware.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer Hardware.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
spellingShingle Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer Hardware.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer Hardware.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Umamageswaran, Kothanda. author.
Pandey, Sheetanshu L. author.
Wilsey, Philip A. author.
SpringerLink (Online service)
Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
description Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
format Texto
topic_facet Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer Hardware.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
author Umamageswaran, Kothanda. author.
Pandey, Sheetanshu L. author.
Wilsey, Philip A. author.
SpringerLink (Online service)
author_facet Umamageswaran, Kothanda. author.
Pandey, Sheetanshu L. author.
Wilsey, Philip A. author.
SpringerLink (Online service)
author_sort Umamageswaran, Kothanda. author.
title Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
title_short Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
title_full Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
title_fullStr Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
title_full_unstemmed Formal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] /
title_sort formal semantics and proof techniques for optimizing vhdl models [electronic resource] /
publisher Boston, MA : Springer US : Imprint: Springer,
publishDate 1999
url http://dx.doi.org/10.1007/978-1-4615-5123-2
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AT pandeysheetanshulauthor formalsemanticsandprooftechniquesforoptimizingvhdlmodelselectronicresource
AT wilseyphilipaauthor formalsemanticsandprooftechniquesforoptimizingvhdlmodelselectronicresource
AT springerlinkonlineservice formalsemanticsandprooftechniquesforoptimizingvhdlmodelselectronicresource
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spelling KOHA-OAI-TEST:1949722018-07-30T23:20:19ZFormal Semantics and Proof Techniques for Optimizing VHDL Models [electronic resource] / Umamageswaran, Kothanda. author. Pandey, Sheetanshu L. author. Wilsey, Philip A. author. SpringerLink (Online service) textBoston, MA : Springer US : Imprint: Springer,1999.engFormal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.1. Introduction -- 1.1 Goals of the Work -- 1.2 Scope of the Work -- 1.3 Notation -- 1.4 Overview of Book -- 2. Related Work -- 2.1 Higher Order Logic -- 2.2 Denotational Semantics -- 2.3 Functional Semantics -- 2.4 Axiomatic Semantics -- 2.5 Petri Nets -- 2.6 Evolving Algebras -- 2.7 Boyer-Moore Logic -- 2.8 Summary -- 3. The Static Model -- 3.1 The VHDL World -- 3.2 Signals -- 3.3 Variables -- 3.4 The Port Hierarchy -- 3.5 Data Types -- 3.6 Expressions -- 3.7 Subprograms -- 3.8 Sequential Statements -- 3.9 Concurrent Statements -- 3.10 Summary -- 4. A Well-Formed VHDL Model -- 4.1 Signals -- 4.2 Variables -- 4.3 The Port Hierarchy -- 4.4 Data Types -- 4.5 Expressions -- 4.6 Sequential Statements -- 4.7 Concurrent Statements -- 4.8 Summary -- 5. The Reduction Algebra -- 5.1 Signal Assignment Statements -- 5.2 Concurrent Statements -- 5.3 The Reduced Form -- 6. Completeness of the Reduced Form -- 6.1 A Brief Overview of PVS -- 6.2 The Specification of the Reduction Algebra in PVS -- 6.3 Signal Assignment Reduction -- 6.4 Completeness -- 6.5 Irreducibility -- 6.6 Conclusion -- 7. Interval Temporal Logic -- 8. The Dynamic Model -- 8.1 Methodology -- 8.2 Evaluation of VHDL Statements -- 8.3 Transaction Lists -- 8.4 The State Space -- 8.5 Waveforms -- 8.6 Observability -- 8.7 Attributes -- 8.8 Conclusions -- 9. Applications of the Dynamic Model -- 9.1 Similarity Revisited -- 9.2 Process Folding -- 9.3 Signal Collapsing -- 9.4 Elimination of Marking -- 9.5 Summary -- 10. A Framework for Proving Equivalences using PVS -- 10.1 The Dynamic Model -- 10.2 Validation of the Semantics -- 10.3 Developing Proofs of Optimizations -- 10.4 Applications to Practical Use -- 11. Conclusions -- 11.1 Contributions of this research -- 11.2 Future Work -- Appendices A— -- A.1 The relation during(b,a) holds -- A.2 The relation finishes(b,a) holds -- A.3 The relation overlaps(a,b) holds -- References.Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.Engineering.Computer hardware.Computer-aided engineering.Electrical engineering.Electronic circuits.Engineering.Circuits and Systems.Computer Hardware.Computer-Aided Engineering (CAD, CAE) and Design.Electrical Engineering.Springer eBookshttp://dx.doi.org/10.1007/978-1-4615-5123-2URN:ISBN:9781461551232

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