Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /

Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /

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Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

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Bibliographic Details
Main Authors: Keating, Michael. author., Bricaud, Pierre. author., SpringerLink (Online service)
Format: Texto biblioteca
Language:eng
Published: Boston, MA : Springer US : Imprint: Springer, 1999
Subjects:Engineering., Computer hardware., Computer-aided engineering., Electrical engineering., Electronic circuits., Circuits and Systems., Computer-Aided Engineering (CAD, CAE) and Design., Electrical Engineering., Computer Hardware.,
Online Access:http://dx.doi.org/10.1007/978-1-4615-5037-2
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id KOHA-OAI-TEST:185631
record_format koha
institution COLPOS
collection Koha
country México
countrycode MX
component Bibliográfico
access En linea
En linea
databasecode cat-colpos
tag biblioteca
region America del Norte
libraryname Departamento de documentación y biblioteca de COLPOS
language eng
topic Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Computer Hardware.
Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Computer Hardware.
spellingShingle Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Computer Hardware.
Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Computer Hardware.
Keating, Michael. author.
Bricaud, Pierre. author.
SpringerLink (Online service)
Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
description Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.
format Texto
topic_facet Engineering.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic circuits.
Engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Computer Hardware.
author Keating, Michael. author.
Bricaud, Pierre. author.
SpringerLink (Online service)
author_facet Keating, Michael. author.
Bricaud, Pierre. author.
SpringerLink (Online service)
author_sort Keating, Michael. author.
title Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
title_short Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
title_full Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
title_fullStr Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
title_full_unstemmed Reuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs /
title_sort reuse methodology manual [electronic resource] : for system-on-a-chip designs /
publisher Boston, MA : Springer US : Imprint: Springer,
publishDate 1999
url http://dx.doi.org/10.1007/978-1-4615-5037-2
work_keys_str_mv AT keatingmichaelauthor reusemethodologymanualelectronicresourceforsystemonachipdesigns
AT bricaudpierreauthor reusemethodologymanualelectronicresourceforsystemonachipdesigns
AT springerlinkonlineservice reusemethodologymanualelectronicresourceforsystemonachipdesigns
_version_ 1756265399055286272
spelling KOHA-OAI-TEST:1856312018-07-30T23:07:45ZReuse Methodology Manual [electronic resource] : For System-on-a-Chip Designs / Keating, Michael. author. Bricaud, Pierre. author. SpringerLink (Online service) textBoston, MA : Springer US : Imprint: Springer,1999.engSilicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.1 Introduction -- 1.1 Goals of This Document -- 1.2 Design for Reuse: The Challenge -- 1.3 Design Reuse: A Business Model -- 2 The System-on-a-Chip Design Process -- 2.1 A Canonical SoC Design -- 2.2 System Design Flow -- 2.3 The Specification Problem -- 2.4 The System Design Process -- 3 System-Level Design Issues: Rules and Tools -- 3.1 The Standard Model -- 3.2 Design for Timing Closure: Logic Design Issues -- 3.3 Design for Timing Closure: Physical Design Issues -- 3.4 Design for Verification: Verification Strategy -- 3.5 System Interconnect and On-Chip Buses -- 3.6 Design for Low Power -- 3.7 Design for Test: Manufacturing Test Strategies -- 3.8 Prerequisites for Reuse -- 4 The Macro Design Process -- 4.1 Design Process Overview -- 4.2 Contents of a Design Specification -- 4.3 Top-Level Macro Design -- 4.4 Subb ock Design -- 4.5 Macro Integration -- 4.6 Soft Macro Productization -- 5 RTL Coding Guidelines -- 5.1 Overview of the Coding Guidelines -- 5.2 Basic Coding Practices -- 5.3 Coding for Portability -- 5.4 Guidelines for Clocks and Resets -- 5.5 Coding for Synthesis -- 5.6 Partitioning for Synthesis -- 5.7 Designing with Memories -- 5.8 Code Profiling -- 6 Macro Synthesis Guidelines -- 6.1 Overview of the Synthesis Problem -- 6.2 Macro Synthesis Strategy -- 6.3 High-Performance Synthesis -- 6.4 RAM and Datapath Generators -- 6.5 Coding Guidelines for Synthesis Scripts -- 7 Macro Verification Guidelines -- 7.1 Overview of Macro Verification -- 7.2 Inspection as Verification -- 7.3 Adversarial Testing -- 7.4 Testbench Design -- 7.5 Timing Verification -- 8 Developing Hard Macros -- 8.1 Overview -- 8.2 Design Issues for Hard Macros -- 8.3 The Hard Macro Design Process -- 8.4 Block Integration for Hard Macros -- 8.5 Productization of Hard Macros -- 8.6 Model Development for Hard Macros -- 8.7 Porting Hard Macros -- 9 Macro Deployment: Packaging for Reuse -- 9.1 Delivering the Complete Product -- 9.2 Contents of the User Guide -- 10 System Integration with Reusable Macros -- 10.1 Integration Overview -- 10.2 Integrating Macros into an Soc Design -- 10.3 Selecting IP -- 10.4 Integrating Memories -- 10.5 Physical Design -- 11 System-Level Verification Issues -- 11.1 The Importance of Verification -- 11.2 The Verification Strategy -- 11.3 Interface Verification -- 11.4 Functional Verification -- 11.5 Application-Based Verification -- 11.6 Gate-Level Verification -- 11.7 Specialized Hardware for System Verification -- 12 Data and Project Management -- 12.1 Data Management -- 12.2 Project Management -- 13 Implementing a Reuse Process -- 13.1 Key Steps in Implementing a Reuse Process -- 13.2 Managing the Transition to Reuse -- 13.3 Organizational Issues in Reuse -- 13.4 Redesign for Reuse: Dealing with Legacy Designs.Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.Engineering.Computer hardware.Computer-aided engineering.Electrical engineering.Electronic circuits.Engineering.Circuits and Systems.Computer-Aided Engineering (CAD, CAE) and Design.Electrical Engineering.Computer Hardware.Springer eBookshttp://dx.doi.org/10.1007/978-1-4615-5037-2URN:ISBN:9781461550372

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