Layout Optimization in VLSI Design [electronic resource] /

Layout Optimization in VLSI Design [electronic resource] /

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Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti­ mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre­ sented in Chapter 1. To reduce the run time, different interconnect plan­ ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.

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Bibliographic Details
Main Authors: Lu, Bing. editor., Du, Ding-Zhu. editor., Sapatnekar, Sachin S. editor., SpringerLink (Online service)
Format: Texto biblioteca
Language:eng
Published: Boston, MA : Springer US : Imprint: Springer, 2001
Subjects:Computer science., Computers., Computer simulation., Computer-aided engineering., Applied mathematics., Engineering mathematics., Electrical engineering., Electronic circuits., Computer Science., Simulation and Modeling., Theory of Computation., Circuits and Systems., Computer-Aided Engineering (CAD, CAE) and Design., Electrical Engineering., Applications of Mathematics.,
Online Access:http://dx.doi.org/10.1007/978-1-4757-3415-7
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id KOHA-OAI-TEST:181064
record_format koha
institution COLPOS
collection Koha
country México
countrycode MX
component Bibliográfico
access En linea
En linea
databasecode cat-colpos
tag biblioteca
region America del Norte
libraryname Departamento de documentación y biblioteca de COLPOS
language eng
topic Computer science.
Computers.
Computer simulation.
Computer-aided engineering.
Applied mathematics.
Engineering mathematics.
Electrical engineering.
Electronic circuits.
Computer Science.
Simulation and Modeling.
Theory of Computation.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Applications of Mathematics.
Computer science.
Computers.
Computer simulation.
Computer-aided engineering.
Applied mathematics.
Engineering mathematics.
Electrical engineering.
Electronic circuits.
Computer Science.
Simulation and Modeling.
Theory of Computation.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Applications of Mathematics.
spellingShingle Computer science.
Computers.
Computer simulation.
Computer-aided engineering.
Applied mathematics.
Engineering mathematics.
Electrical engineering.
Electronic circuits.
Computer Science.
Simulation and Modeling.
Theory of Computation.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Applications of Mathematics.
Computer science.
Computers.
Computer simulation.
Computer-aided engineering.
Applied mathematics.
Engineering mathematics.
Electrical engineering.
Electronic circuits.
Computer Science.
Simulation and Modeling.
Theory of Computation.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Applications of Mathematics.
Lu, Bing. editor.
Du, Ding-Zhu. editor.
Sapatnekar, Sachin S. editor.
SpringerLink (Online service)
Layout Optimization in VLSI Design [electronic resource] /
description Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti­ mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre­ sented in Chapter 1. To reduce the run time, different interconnect plan­ ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.
format Texto
topic_facet Computer science.
Computers.
Computer simulation.
Computer-aided engineering.
Applied mathematics.
Engineering mathematics.
Electrical engineering.
Electronic circuits.
Computer Science.
Simulation and Modeling.
Theory of Computation.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical Engineering.
Applications of Mathematics.
author Lu, Bing. editor.
Du, Ding-Zhu. editor.
Sapatnekar, Sachin S. editor.
SpringerLink (Online service)
author_facet Lu, Bing. editor.
Du, Ding-Zhu. editor.
Sapatnekar, Sachin S. editor.
SpringerLink (Online service)
author_sort Lu, Bing. editor.
title Layout Optimization in VLSI Design [electronic resource] /
title_short Layout Optimization in VLSI Design [electronic resource] /
title_full Layout Optimization in VLSI Design [electronic resource] /
title_fullStr Layout Optimization in VLSI Design [electronic resource] /
title_full_unstemmed Layout Optimization in VLSI Design [electronic resource] /
title_sort layout optimization in vlsi design [electronic resource] /
publisher Boston, MA : Springer US : Imprint: Springer,
publishDate 2001
url http://dx.doi.org/10.1007/978-1-4757-3415-7
work_keys_str_mv AT lubingeditor layoutoptimizationinvlsidesignelectronicresource
AT dudingzhueditor layoutoptimizationinvlsidesignelectronicresource
AT sapatnekarsachinseditor layoutoptimizationinvlsidesignelectronicresource
AT springerlinkonlineservice layoutoptimizationinvlsidesignelectronicresource
_version_ 1756264772153638912
spelling KOHA-OAI-TEST:1810642018-07-30T23:01:07ZLayout Optimization in VLSI Design [electronic resource] / Lu, Bing. editor. Du, Ding-Zhu. editor. Sapatnekar, Sachin S. editor. SpringerLink (Online service) textBoston, MA : Springer US : Imprint: Springer,2001.engIntroduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti­ mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre­ sented in Chapter 1. To reduce the run time, different interconnect plan­ ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.1. Integrated Floorplanning and Interconnect Planning -- 2. Interconnect Planning -- 3. Modern Standard-cell Placement Techniques -- 4. Non-Hanan Optimization for Global VLSI Interconnect -- 5. Techniques for Timing-Driven Routing -- 6. Interconnect Modeling and Design with Consideration of Inductance -- 7. Modeling and Characterization of IC Interconnects and Packagings for the Signal Intergrity Verification on High-Performance VLSI Circuits -- 8. Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area.Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti­ mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre­ sented in Chapter 1. To reduce the run time, different interconnect plan­ ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques.Computer science.Computers.Computer simulation.Computer-aided engineering.Applied mathematics.Engineering mathematics.Electrical engineering.Electronic circuits.Computer Science.Simulation and Modeling.Theory of Computation.Circuits and Systems.Computer-Aided Engineering (CAD, CAE) and Design.Electrical Engineering.Applications of Mathematics.Springer eBookshttp://dx.doi.org/10.1007/978-1-4757-3415-7URN:ISBN:9781475734157

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