Morphological Image Processing: Architecture and VLSI design [electronic resource] /
Summary Based on the experiences of past designs and the outcome of recent studies in the comparisons of low-level image processing architectures, a pipelined system for real time low-image processing has been designed and realized in CMOS technology. To minimize design pitfalls, a study was performed to the details of the design solutions that have been found in embodimentsof the three main architectural groups of image processing; the Square Processor Arrays, the Linear Processor Arrays and the Pipelines. This is reflected in a theoretical model. As the design is based on bitplane-wise processing of images, research was performed on the principles ofCellularLogic Processing of two dimensional images. of binary A methodology has been developed that is based on the transformation images using sets of Hit-or-Miss masks. This method appeared to be extendable to higher dimensional images. A theoretical model for the generation of break-point conditions in high dimensional images has been developed, and applied up to dimension three.
Main Authors: | , |
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Format: | Texto biblioteca |
Language: | eng |
Published: |
Boston, MA : Springer US : Imprint: Springer,
1992
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Subjects: | Engineering., Image processing., Electrical engineering., Electronic circuits., Circuits and Systems., Image Processing and Computer Vision., Electrical Engineering., Signal, Image and Speech Processing., |
Online Access: | http://dx.doi.org/10.1007/978-1-4615-2804-3 |
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